1. Field of the Invention
The technical field of this invention lies with output buffer circuits utilized to couple a multiplicity of logic circuits to a common bus. More particularly, this invention is related to means for ensuring high speed switching of said bus and in particular to preventing that power-draining switch-delaying transient state where a buffer's pulldown (current sinking) circuitry is activated at the wrong time. More particularly yet, it is related to that category of subcircuits known generically as "Miller Killers," the purpose of which is to ensure that the output pulldown transistor of said buffer is subject to neither spurious turn-on nor delay in turning off caused by Miller Current-generated base current. The term "Miller Current" is generally associated with the parasitic current affecting the performance of bipolar output pulldown transistors. When a MOS transistor is the output pulldown transistor, the delay mechanism is different; nevertheless, both are caused by the propagation of a parasitic current and the overall effect remains the same, namely, a delay in the turn-off of that pulldown transistor. For the purpose of the following discussion, this parasitic current will be identified as a Miller Current. It is to be understood, however, that the present invention is directed to preventing delays in pulldown transistor turn-off, regardless of whether that pulldown transistor is a bipolar or a MOS device. Most particularly, the present invention relates to a subcircuit designed to kill the Miller Current during the period that powerdown of said buffers and associated circuitry disables traditional Miller Killer devices while leaving it possible for Miller Current to cause spurious current sinking at pulldown transistors. The powerdown situation where the present invention finds its greatest potential application is that where a specific buffer is powered down, yet still coupled to a common bus being acted on by other buffers which are not powered down. Under those circumstances Miller Current generated at the output of the powered-down buffer will not be discharged by the MK circuits previously disclosed.
The Power Down Miller Killer circuit which is the subject of this invention has applicability to bistate and tristate BiCMOS output buffers. In its preferred embodiment, it is comprised of NMOS and PMOS transistors and shields the bipolar or MOS output pulldown transistors of a bistate or tristate BiCMOS output buffer from Miller Current. More particularly, the preferred embodiment relates to the BiCMOS output buffer circuit described in the related patent application identified above. Such output buffer circuits incorporate the low power requirements, high input impedance, and high speed advantages of NMOS and PMOS transistors along with the high current amplification and low output impedance advantages of bipolar transistors.
2. Description of Prior Art
The switching conditions hitherto identified as requiring Miller Killer remediation are: 1) an active-low to active-high output buffer transition; 2) an inactive-mode (high Z) output buffer having its output forced high (e.g., due to the L.fwdarw.H switching action of another output buffer coupled to the bus); 3) an output buffer being switched from active-high to its inactive mode. In each case the goal has been to prevent Miller Current from going to ground through the base-emitter junction of the pulldown transistor, the effect which causes or prolongs unwanted conduction of the pulldown transistor. Apart from the deleterious effects of having the pulldown transistor conducting when it should be blocking, significant switching delays can be introduced. The problem can be overcome by providing a low-resistance path to ground from the control node of the pulldown transistor. The general approach has been to couple the control node of the output pulldown transistor to ground (low potential power rail) across a transistor (the MK transistor) coupled to circuitry which turns it on during the period that Miller Current would otherwise cause an unwanted base current in the output pulldown transistor. Because of the variety of circumstances under which MK circuits are required, a particular buffer circuit may have a multiplicity of MK transistors, each being turned on upon a particular switching sequence.
The earliest-issued MK patent is that of Bechdolt, U.S. Pat. No. 4,321,490 (1982): "Transistor Logic Output for Reduced Power Consumption and Increased Speed During Low to High Transition." Bechdolt discloses an AC Miller Killer (ACMK) circuit addressing the switching delay and power drain associated with a low to high (L.fwdarw.H) output transition of an active output buffer. In its L output state just prior to the L.fwdarw.H transition, the buffer is sinking current through its pulldown transistors. The transition requires the turnon of the pullup transistors so that they source current to V.sub.OUT from a high potential power rail V.sub.CCN and for the concurrent turnoff of the pulldown transistors so that they block. Included in the turnoff transient of the pulldown transistors is the time required to charge the Miller Capacitance by the pullup transistors, which leads to an effective postponement of blocking by the pulldown transistor. The parasitic current into the pulldown transistor retards the turnoff of that transistor and provides a window during which both pullup and pulldown transistors are conducting, coupling V.sub.CCN to GNDN. This causes a significant power drain and prolongs the time required for the current-sourcing circuit to complete the L.fwdarw.H switch at the bus. The MK transistor of Bechdolt is a bipolar transistor coupled between the control node of the pulldown transistor and GNDN. Its base is coupled to V.sub.out through a capacitor which is sufficiently large that, upon the L.fwdarw.H output transition which provides the Miller Current, it passes through enough capacitive current to turn on the MK transistor. This guarantees that the L.fwdarw.H output transition which causes Miller Current also turns on the ACMK transistor which pulls the control node of the pulldown transistor to GNDN and ensures that the turnoff of that transistor is not delayed.
The MK circuit of Ferris, U.S. Pat. No. 4,311,927 (1982), "Transistor Logic Device with Reduced Output Capacitance," is directed at Miller Current generated at the output pulldown transistors of inactive output buffers during L.fwdarw.H switching of the bus. It alleviates the problem arising from the fact that a tristate output buffer in the so-called "high Z" state still--by virtue of its large Miller Capacitance--presents to the bus a fairly low ac impedance. Thus when the output of an inactive buffer is forced high (by an L.fwdarw.H transition of an active buffer connected to the common bus) a significant Miller Current will flow. The results are as before--a potential power drain through the turned-on output pulldown transistor (which can potentially occur for each of the inactive output buffers connected to the bus) and a delay in the completion of the L.fwdarw.H transition of the bus. The MK transistor of Ferris is also coupled between the control node of the output pulldown transistor and GNDN. Its base is coupled to the enable gate in such a way that when the OE input is Low-placing the buffer in its inactive, high Z mode--the MK transistor is on, providing a low impedance path to ground from the output pulldown transistor's node. (To achieve this, two additional transistors--beyond the MK transistor itself--must be included as intermediaries between the OE input and the base node of the MK transistor.) Since the MK transistor of Ferris is maintained conducting throughout the time the buffer is in its high Z state, it is designated a dc Miller Killer (DCMK). Subsequent developments of the DCMK are described in Vazehgoo, U.S. Pat. No. 4,649,297 (1987), "TTL Circuits for Generating Complementary Signals" and in Yarbrough et al., U.S. Pat. No. 5,051,623 (1991), "TTL Tristate Circuit for Output Pulldown Transistor."
The pending U.S. Patent application of Ward, Ser. No. 881,540, filed May 12, 1992, addresses the third case: the transient when the output buffer is making a transition from the L active state to the inactive high Z state. Like the ACMK, the MK action of Ward is triggered by the switch; to distinguish it from the ACMK operative in just the active state, it is designated as Z/ACMK.
Unfortunately, none of the prior art Miller Killer circuits provides Miller Current protection when the output buffer circuit is powered down, that is, when--for whatever reason--the dc voltage V.sub.CC falls below a certain critical threshold. This is a serious lapse, since the current sinking action of the pulldown transistor can still be activated, even for V.sub.CC below this level. This can then give rise to bus loading when a particular output buffer or the entire multiplicity of buffers is powered down. More practically, it presents a potential loading of the common bus when individual buffers have been powered down while the extended circuit continues to operate, with L.fwdarw.H transitions continuing on the bus. What is needed is a Miller Killer circuit which is triggered by low V.sub.CC levels and continues to provide protection for as long as the buffer is powered down.